1. Field
The present example embodiments of inventive concepts relate to a semiconductor memory device.
2. Description of the Related Art
In a data read operation, a large-capacity nonvolatile memory device, such as an electrically erasable and programmable read only memory (EEPROM), reads out data simultaneously from a plurality of memory cells in each page and serially outputs the read data. In a data write operation, the nonvolatile memory device serially inputs data to the memory cells on a page-by-page basis while writing the data simultaneously to a plurality of memory cells in each page. For this data read or write operation, a plurality of column lines, (i.e. bit lines) are respectively connected to a plurality of page buffers, each having a data latch that temporarily latches read data or data to be written.
A NAND-type EEPROM writes data to memory cells in one row from among a plurality of memory cells arranged in a matrix of rows and columns. Generally, each memory cell of the NAND-type EEPROM is a floating gate N-channel metal oxide semiconductor (MOS) transistor formed within a P-type well in a surface of a semiconductor substrate. Each floating gate N-channel MOS transistor includes source and drain regions separated from each other in a P-type well, a tunnel oxide film on a channel region between the source region and the drain region, a polycrystalline silicon floating gate on the tunnel oxide film, and a control gate of a dielectric insulating film on the floating gate.
In one column of the matrix, memory cells are connected in series to form a NAND cell string. A first select transistor is inserted between an end of the NAND cell string and a bit line, and a second select transistor is inserted between the other end of the NAND cell string and a common source line.
In a data write operation, the first select transistor is turned on while the second select transistor is turned off. If data [0] is to be written, a voltage of 0 V is applied to the bit line. If data [1] is to be written (if an erase state is to be maintained), a power supply voltage VCC is applied to the bit line. A program voltage Vpgm is applied to a word line WL connected to a selected memory cell, and a pass voltage Vpass is applied to a word line WL connected to an unselected memory cell.
Accordingly, in a memory cell to which the data [0] should be written, a high voltage is applied to between a channel and a control gate. The high voltage causes injection of electrons from the channel to a floating gate and shifts a threshold voltage of the memory cell from a negative voltage to a positive voltage.
In a memory cell to which the data [1] should be written, a voltage lower than the voltage for the memory cell to which the data [0] is written is applied between a channel and a control gate. Therefore, the injection of electrons to a floating gate is reduced, and a threshold voltage of the memory cell is maintained at the negative voltage.
However, the threshold voltage of the memory cell can shift. This shift in the threshold voltage is caused by capacitive coupling resulting from a change in a threshold voltage of an adjacent memory cell.
The capacitive coupling between adjacent nonvolatile memory cells occurs most noticeably between a pair of adjacent memory cells written at different times. For example, a first memory cell may be written by applying a voltage corresponding to one data set to a floating gate of the first memory cell. Then, an adjacent memory cell may be written by applying a voltage corresponding to a second data set to a floating gate of the adjacent memory cell. When the adjacent memory cell is written, a threshold voltage of the first memory cell during a read operation may appear different from a threshold voltage of the first memory cell during the write operation. This phenomenon results from a shift in a threshold voltage of the adjacent memory cell, which is coupled to the first memory cell, during the write operation. The capacitive coupling from the adjacent memory cell may shift the threshold voltage of the first memory cell during the read operation and cause an error in reading the data stored in the first memory cell.
As memory cells become smaller in size, the gap between bit lines is reduced, which in turn, increases the capacitive coupling between adjacent nonvolatile memory cells. A NAND-type EEPROM designed to reduce the effect of the capacitive coupling is disclosed in Japanese Patent Publication No. 2010-515203 (Patent Literature 1).
A nonvolatile semiconductor memory device disclosed in the Patent Literature 1 reads out data from a nonvolatile memory cell connected to a selected word line (e.g., a word line WLn) while compensating for capacitive coupling between adjacent floating gates. The compensating of the capacitive coupling includes detecting the state of a nonvolatile memory cell connected to an adjacent word line (e.g., a word line Wn+1) and determining the effect of the state on the capacitive coupling between the floating gates.
Specifically, if the nonvolatile memory cell connected to the word line WLn is a memory cell to be read, the nonvolatile memory cell connected to the word line WLn+1 is selected, and data is written to a latch of a page buffer. Based on the data written to the latch, the latch of the page buffer judges data stored in the nonvolatile memory cell connected to the word line WLn+1 (for example, determines whether the data stored in the nonvolatile memory cell is data [1] or data [0] (if the stored data is 2-value data)).
The data read from the nonvolatile memory cell connected to the word line WLn+1 is limited to two states (state A in the case of the data [1] and state B in the case of the data [0]).
In an operation of reading data from the nonvolatile memory cell connected to the word line WLn, a read voltage Vread is applied to the word line WLn, and a read voltage VreadX corresponding to the state A is applied to the word line WLn+1. Then, a first read operation is performed. Next, the read voltage Vread is applied to the word line WLn, and the read voltage VreadX corresponding to the state B is applied to the word line WLn+1. Then, a second read operation is performed.
In the above two data read operations, if the nonvolatile memory cell connected to the word line WLn+1 is in the state A, a result corresponding to the state B is ignored. If the nonvolatile memory cell connected to the word line WLn+1 is in the state B, a result corresponding to the state A is ignored.
In this way, the nonvolatile semiconductor memory device disclosed in the Patent Literature 1 reads out data from the nonvolatile memory cell connected to the word line WLn while compensating for the capacitive coupling between the floating gates. However, since the data is judged twice for the states A and B, it takes additional time to judge the nonvolatile memory cell connected to the selected word line Wn.
In addition, a threshold voltage of the nonvolatile memory cell connected to the word line WLn+1 is limited to two states A and B. Therefore, although different nonvolatile memory cells have different threshold voltages in each state, their threshold voltages are limited to one state. A threshold voltage of an adjacent memory cell is not reflected in the capacitive coupling between floating gates. This reduces the accuracy of compensating for the capacitive coupling between floating gates.